Semiconductor memory device, memory controller, and data processing system including these

ABSTRACT

In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation Application of U.S. patentapplication Ser. No. 13/160,198 filed Jun. 14, 2011, which claimspriority from Japanese Patent Application No. 2010-135822, filed Jun.15, 2010, the contents of all of which are incorporated herein byreference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, a memorycontroller, and a data processing system including these, and moreparticularly relates to a semiconductor memory device that requiresholding of data by a refresh operation, a memory controller thatcontrols the semiconductor memory device, and a data processing systemincluding the semiconductor memory device and the memory controller.

2. Description of Related Art

A DRAM (Dynamic Random Access Memory) as one of representativesemiconductor memory devices has a memory cell constituted by onetransistor and one capacitor. Therefore, an area occupied per one memorycell is small, and the DRAM has excellent characteristics such that ahigh integration can be obtained. On the other hand, because datawritten in the memory cell is lost after a predetermined time, it isnecessary to periodically perform a refresh operation.

In the refresh operation, many sense amplifiers are simultaneouslyactivated, and therefore a relatively large current flows. By takingthis point into consideration, Japanese Patent Application Laid-open No.2000-30439 proposes a method of suppressing a peak current by shifting atiming of performing a refresh operation in each bank when a refreshcommand is issued from outside. This method can be easily achieved byindependently providing in each bank a transmission path of a refreshsignal within a chip.

Meanwhile, in recent years, there has been proposed a method ofconfiguring a semiconductor memory device by integrating a frontendportion and a backend portion of a DRAM in separate chips and bystacking these chips (Japanese Patent Application Laid-open No.2007-157266). According to this method, plural core chips in each ofwhich backend portions are integrated have an increased occupied areathat can be allocated to a memory core. Therefore, the memory capacityper one chip (per one core chip) can be increased. Meanwhile, aninterface chip that has frontend portions integrated therein and iscommon to plural core chips can be manufactured by a process that isdifferent from a process of manufacturing the memory core. Accordingly,a circuit can be formed by high-speed transistors. Further, becauseplural core chips can be allocated to one interface chip, it is possibleto provide a semiconductor memory device having a very large capacityand high speed as a whole.

In this type of semiconductor memory device, it is very important tomanufacture core chips by the same mask to reduce the manufacturingcost.

However, when core chips are manufactured by the same mask, these corechips mutually have the same circuit configurations. Therefore, itbecomes difficult to selectively send a signal to a specific core chipfrom an interface chip. Consequently, in this type of semiconductormemory device, it is difficult to selectively perform a refreshoperation by providing plural transmission paths of a refresh signal asdescribed in Japanese Patent Application Laid-open No. 2000-30439.

SUMMARY

In one embodiment, there is provided a semiconductor memory device thatincludes a semiconductor memory device comprising: a plurality of corechips assigned to mutually different chip information, each of the corechips comprising a plurality of memory cells that require a refreshoperation to hold data stored therein; and an interface chip thatreceives a refresh command and first address information supplied fromoutside, the first address information relating to the chip information,the interface chip generates at least one time of a refresh controlsignal based on the refresh command, and supplies the refresh controlsignal and the first address information in common to the core chips,wherein each of the core chips includes: a determining circuit thatdetermines whether the first address information supplied from theinterface chip selects a respective core chip; and a refresh controlcircuit that performs the refresh operation to the memory cell includedin the respective core chip in response to the refresh control signalwhen the determining circuit determines that the first addressinformation selects the respective core chip.

In another embodiment, there is provided a memory controller thatincludes a memory controller that controls a semiconductor memory deviceincluding an interface chip and a plurality of core chips, the memorycontroller comprising: a first circuit that issues a refresh command ata plurality of times during a predetermined period; and a second circuitthat issues address information that selects the core chips along withthe refresh command.

In still another embodiment, there is provided a memory system thatincludes a memory system comprising: a semiconductor memory devicecomprising a plurality of core chips and an interface chip that controlsthe core chips, each of the core chips including a plurality of memorycells and a refresh control circuit that performs refresh operation tothe memory cells; and a memory controller that controls thesemiconductor memory device, wherein the memory controller includes: afirst circuit that issues a refresh command at a plurality of timesduring a predetermine period; and a second circuit that issues addressinformation that selects the core chips along with the refresh command,the interface chip includes a refresh-control-signal generation circuitthat receives the refresh command and the address information that aresupplied from the memory controller and generates a refresh controlsignal in response to the refresh command, the interface chip suppliesthe refresh control signal and the address information in common to thecore chips, each of the core chips includes a determining circuit thatdetermines whether the address information selects a respective corechip, and the refresh control circuit performs the refresh operation tothe memory cell in response to the refresh control signal when theaddress information selects the respective core chip.

According to the present invention, because each of the core chipsperforms a refresh operation by referring to the address information, arefresh operation can be selectively instructed to each of the corechips even when the refresh control signal is supplied in common toplural core chips. With this configuration, a peak current in therefresh operation can be reduced. Further, even when a certain core chipis performing a refresh operation, an arbitrary command (such as anactive command) apart from a refresh command can be issued to other corechips that are not supposed to be refreshed. Therefore, the issuingefficiency of commands can be increased. Because a memory capacity to berefreshed by a refresh command for one time becomes small, a shortestissuing interval of a refresh command can be shortened even when it isnecessary to comply with specifications such that a shortest issuinginterval of a refresh command becomes long when a memory capacity islarge.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic cross-sectional view for explaining a structure ofa semiconductor memory device 10 according to the preferred embodimentof the present invention;

FIGS. 2A to 2C are diagram for explaining various types of throughsilicon vias TSV provided in a core chip;

FIG. 3 is a cross-sectional view showing a structure of the throughsilicon via TSV of the type shown in FIG. 2A;

FIG. 4 is a block diagram showing a circuit configuration of thesemiconductor memory device 10;

FIG. 5 is a schematic diagram for explaining a bank configuration of thesemiconductor memory device 10;

FIG. 6 is a diagram showing an extract of circuits relevant togeneration of a layer address;

FIG. 7 is a circuit diagram of a refresh-control-signal generationcircuit 100;

FIG. 8 is a circuit diagram of a counter circuit 110;

FIG. 9 is a timing chart for explaining an operation of the countercircuit 110;

FIG. 10 is a timing diagram for explaining an operation of therefresh-control-signal generation circuit 100 when a first operationmode is selected;

FIG. 11 is a timing diagram for explaining an operation of therefresh-control-signal generation circuit 100 when a second operationmode is selected;

FIG. 12 is a circuit diagram of a refresh control circuit 200;

FIG. 13 is a timing diagram for explaining an operation of the refreshcontrol circuit 200 when the first operation mode is selected;

FIG. 14 is a timing diagram for explaining an operation of the refreshcontrol circuit 200 when the second operation mode is selected;

FIG. 15 is a timing diagram for explaining an operation of arefresh-control-signal dividing circuit 300;

FIG. 16 is a circuit diagram of a refresh counter 61 b;

FIG. 17 is a timing diagram for explaining an operation of the refreshcounter 61 b;

FIG. 18 is a timing diagram for explaining an operation of thesemiconductor memory device 10 when the first operation mode isselected;

FIG. 19 is a timing diagram for explaining an operation of thesemiconductor memory device 10 when the second operation mode isselected;

FIG. 20 is a circuit diagram of a layer address comparison circuit 47according to a modification;

FIG. 21 is a timing diagram for explaining an operation in a doubleslice mode;

FIG. 22 is a circuit diagram of a refresh-control-signal generationcircuit 100 a used in a second embodiment;

FIG. 23 is a circuit diagram of a refresh-control-signal generationcircuit 200 a used in the second embodiment;

FIG. 24 is a circuit diagram of a layer address comparison circuit 47 aused in the second embodiment; and

FIG. 25 is a diagram showing a configuration of a data processing systemthat uses the semiconductor memory device 10.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Preferred embodiments of the present invention will be explained belowin detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view provided to explain thestructure of a semiconductor memory device 10 according to the preferredembodiment of the present invention.

As shown in FIG. 1, the semiconductor memory device 10 according to thisembodiment includes 8 core chips CC0 to CC7, an interface chip IF, andan interposer IP that are laminated. The 8 core chips CC0 to CC7 have asame function and structure and are manufactured using a samemanufacture mask. The interface chip IF is manufactured using amanufacture mask different from that of the core chips. The core chipsCC0 to CC7 and the interface chip IF are semiconductor chips including asilicon substrate and are electrically connected to adjacent chips in avertical direction through plural Through Silicon Vias (TSV) penetratingthe silicon substrate. The interposer IP is a circuit board that is madeof a resin, and plural external terminals (solder balls) SB are formedin a back surface IPb of the interposer IP.

Each of the core chips CC0 to CC7 is a semiconductor chip which consistsof circuit blocks other than a so-called front end unit (front endfunction) performing a function of an interface with an external deviceof the semiconductor memory device through an external terminal amongcircuit blocks included in a 1 Gb DDR3 (Double Data Rate 3)-type SDRAM(Synchronous Dynamic Random Access Memory). The SDRAM is a well-knownand common memory chip that includes the front end unit and a so-calledback end unit having a plural memory cells. The SDRAM operates even as asingle chip and is capable of communicating directly with a memorycontroller. That is, each of the core chips CC0 to CC7 is asemiconductor chip where only the circuit blocks belonging to the backend unit are integrated in principle. A parallel-serial convertingcircuit (data latch circuit) and a DLL (Delay Locked Loop) circuit arecircuit blocks that are included in the front end unit. Theparallel-serial converting circuit (data latch circuit) performsparallel/serial conversion on input/output data between a memory cellarray and a data input/output terminal. The DLL circuit controlsinput/output timing of data. The interface chip IF is a semiconductorchip in which only the front end unit is integrated. Accordingly, anoperation frequency of the interface chip is higher than an operationfrequency of the core chip. Since the circuits that belong to the frontend unit are not included in the core chips CC0 to CC7, the core chipsCC0 to CC7 cannot be operated as the single chips, except for when thecore chips are operated in a wafer state for a test operation in thecourse of manufacturing the core chips. The interface chip IF is neededto operate the core chips CC0 to CC7. Accordingly, the memoryintegration of the core chips is denser than the memory integration of ageneral single chip. In the semiconductor memory device 10 according tothis embodiment, the interface chip has a front end function forcommunicating with the external device at a first operation frequency,and the plural core chips have a back end function for communicatingwith only the interface chip at a second operation frequency lower thanthe first operation frequency. Accordingly, each of the plural corechips includes a memory cell array that stores plural information, and abit number of plural read data for each I/O (DQ) that are supplied fromthe plural core chips to the interface chip in parallel is plural andassociated with a one-time read command provided from the interface chipto the core chips. In this case, the plural bit number corresponds to aprefetch data number to be well-known.

The interface chip IF functions as a common front end unit for the eightcore chips CC0 to CC7. Accordingly, all external accesses are performedthrough the interface chip IF and inputs/outputs of data are alsoperformed through the interface chip IF. In this embodiment, theinterface chip IF is disposed between the interposer IP and the corechips CC0 to CC7. However, the position of the interface chip IF is notrestricted in particular, and the interface chip IF may be disposed onthe core chips CC0 to CC7 and may also be disposed on the back surfaceIPb of the interposer IP. When the interface chip IF is disposed on thecore chips CC0 to CC7 in a face-down manner or is disposed on the backsurface IPb of the interposer IP in a face-up manner, the throughsilicon vias TSV do not need to be provided in the interface chip IF.The interface chip IF may be interposed between the two interposers IP.

The interposer IP functions as a rewiring substrate to increase anelectrode pitch and secures mechanical strength of the semiconductormemory device 10. That is, an electrode 91 that is formed on a topsurface IPa of the interposer IP is drawn to the back surface IPb via athrough-hole electrode 92 and the pitch of the external terminals SB isenlarged by the rewiring layer 93 provided on the back surface IPb. InFIG. 1, only the two external terminals SB are shown. In actuality,however, three or more external terminals are provided. The layout ofthe external terminals SB is the same as that of the DDR3-type SDRAMthat is determined by regulation. Accordingly, the semiconductor memorydevice can be treated as one DDR3-type SDRAM from the externalcontroller.

As shown in FIG. 1, a top surface of the uppermost core chip CC0 iscovered by an NCF (Non-Conductive Film) 94 and a lead frame 95. Gapsbetween the core chips CC0 to CC7 and the interface chip IF are filledwith an underfill 96 and surrounding portions of the gaps are covered bya sealing resin 97. Thereby, the individual chips are physicallyprotected.

When most of the through silicon vias TSV provided in the core chips CC0to CC7 are two-dimensionally viewed from a lamination direction, thatis, viewed from an arrow A shown in FIG. 1, the through silicon vias TSVare short-circuited from the through silicon vias TSV of other layersprovided at the same position. That is, as shown in FIG. 2A, thevertically disposed through silicon vias TSV1 that are provided at thesame position in plain view are short-circuited, and one wiring line isconfigured by the through silicon via TSV1. The through silicon via TSV1that are provided in the core chips CC0 to CC7 are connected to internalcircuits 4 in the core chips, respectively. Accordingly, input signals(command signal, address signal, etc.) that are supplied from theinterface chip IF to the through silicon vias TSV1 shown in FIG. 2A arecommonly input to the internal circuits 4 of the core chips CC0 to CC7.Output signals (data etc.) that are supplied from the core chips CC0 toCC7 to the through silicon via TSV1 are wired-ORed and input to theinterface chip IF.

Meanwhile, as shown in FIG. 2B, a part of through silicon vias TSV arenot directly connected to the through silicon via TSV2 of other layersprovided at the same position in plain view but are connected to thethrough silicon via TSV2 of other layers through the internal circuits 5provided in the core chips CC0 to CC7. The internal circuits 5 that areprovided in the core chips CC0 to CC7 are cascade-connected through thethrough silicon via TSV2. This kind of through silicon via TSV2 is usedto sequentially transmit predetermined information to the internalcircuits 5 provided in the core chips CC0 to CC7. This information whichis layer address information (chip information) is described below.

Another through silicon via TSV group is short-circuited from thethrough silicon vias TSV of other layer provided at the differentposition in plain view, as shown in FIG. 2C. With respect to this kindof through silicon via TSV group 3, internal circuits of the core chipsCC0 to CC7 are connected to the through silicon via TSV3a provided atthe predetermined position P in plain view. Thereby, information can beselectively input to the internal circuits 6 provided in the core chips.This information which is defective chip information is described below.

As such, three types of the through silicon vias TSV exist and areprovided in the core chips CC0 to CC7. The three types of TSVs TSV1 toTSV3 are shown in FIGS. 2A to 2C, respectively. As described above, mostof the through silicon vias TSV are of a type shown in FIG. 2A, and anaddress signal, a command signal, and a clock signal are supplied fromthe interface chip IF to the core chips CC0 to CC7, through the throughsilicon via TSV1 shown in FIG. 2A. Read data and write data are input toand output from the interface chip IF through the through silicon viaTSV1 shown in FIG. 2A. Meanwhile, the through silicon via TSV2 andthrough silicon via TSV3 shown in FIGS. 2B and 2C, respectively, areused to provide individual information to the core chips CC0 to CC7having the same structure.

FIG. 3 is a cross-sectional view illustrating the structure of thethrough silicon via TSV1 of the type shown in FIG. 2A.

As shown in FIG. 3, the through silicon via TSV1 is provided topenetrate a silicon substrate 80 and an interlayer insulating film 81provided on a surface of the silicon substrate 80. Around the throughsilicon via TSV1, an insulating ring 82 is provided. Thereby, thethrough silicon via TSV1 and a transistor region are insulated from eachother. In an example shown in FIG. 3, two insulating rings 82 areprovided. Thereby, capacitance between the through silicon via TSV1 andthe silicon substrate 80 is reduced.

An end 83 of the through silicon via TSV1 at the back surface of thesilicon substrate 80 is covered by a back surface bump 84. The backsurface bump 84 is an electrode that contacts a surface bump 85 providedin a core chip of a lower layer. The surface bump 85 is connected to anend 86 of the through silicon via TSV1, through plural pads P0 to P3provided in wiring layers L0 to L3 and plural through-hole electrodesTH1 to TH3 connecting the pads to each other. Thereby, the surface bump85 and the back surface bump 84 that are provided at the same positionin plain view are short-circuited. Connection with internal circuits(not shown in the drawings) is performed through internal wiring lines(not shown in the drawings) drawn from the pads P0 to P3 provided in thewiring layers L0 to L3.

FIG. 4 is a block diagram illustrating the circuit configuration of thesemiconductor memory device 10.

As shown in FIG. 4, the external terminals that are provided in theinterposer IP include clock terminals 11 a and 11 b, a clock enableterminal 11 c, command terminals 12 a to 12 e, an address terminal 13, adata input/output terminal 14, data strobe terminals 15 a and 15 b, acalibration terminal 16, and power supply terminals 17 a and 17 b. Allof the external terminals are connected to the interface chip IF and arenot directly connected to the core chips CC0 to CC7, except for thepower supply terminals 17 a and 17 b.

First, a connection relationship between the external terminals and theinterface chip IF performing the front end function and the circuitconfiguration of the interface chip IF will be described.

The clock terminals 11 a and 11 b are supplied with external clocksignals CK and /CK, respectively, and the clock enable terminal 11 c issupplied with a clock enable signal CKE. The external clock signals CKand /CK and the clock enable signal CKE are supplied to a clockgenerating circuit 21 provided in the interface chip IF. A signal where“/” is added to a head of a signal name in this specification indicatesan inversion signal of a corresponding signal or a low-active signal.Accordingly, the external clock signals CK and /CK are complementarysignals. The clock generating circuit 21 generates an internal clocksignal ICLK, and the generated internal clock signal ICLK is supplied tovarious circuit blocks in the interface chip IF and is commonly suppliedto the core chips CC0 to CC7 through the through silicon vias TSV.

A DLL circuit 22 is included in the interface chip IF and aninput/output clock signal LCLK is generated by the DLL circuit 22. Theinput/output clock signal LCLK is supplied to an input/output buffercircuit 23 included in the interface chip IF. A DLL function is used tocontrol the front end unit by using the signal LCLK synchronized with asignal of the external device, when the semiconductor memory device 10communicates with the external device. Accordingly, DLL function is notneeded for the core chips CC0 to CC7 as the back end.

The command terminals 12 a to 12 e are supplied with a row-addressstrobe signal /RAS, a column address strobe signal /CAS, a write enablesignal /WE, a chip select signal /CS, and an on-die termination signalODT. These command signals are supplied to a command input buffer 31that is provided in the interface chip IF. The command signals suppliedto the command input buffer 31 are further supplied to a command decoder32. The command decoder 32 is a circuit that holds, decodes, and countsthe command signals in synchronization with the internal clock ICLK andgenerates various internal commands ICMD. The generated internal commandICMD is supplied to the various circuit blocks in the interface chip IFand is commonly supplied to the core chips CC0 to CC7 through thethrough silicon vias TSV.

Further, the interface chip IF includes a refresh-control-signalgeneration circuit 100, and when an auto-refresh command (hereinafter,simply “refresh command”) is input (supplied) to the command decoder 32from outside of the semiconductor memory device 10, the command decoder32 supplies an internal refresh command REFa to the inside of therefresh-control-signal generation circuit 100. Although details thereofare described later, when a first operation mode is selected, therefresh-control-signal generation circuit 100 directly supplies theinternal refresh command REFa for one time as a refresh control signalREFb for one time to the core chips CC0 to CC7, and when a secondoperation mode is selected, the refresh-control-signal generationcircuit 100 generates the refresh control signal REFb for plural timesbased on the internal refresh command REFa for one time, and functionsto supply the generated refresh control signals REFb to the core chipsCC0 to CC7. An operation mode is assigned based on a mode selectionsignal PRA that is supplied from a mode register 42.

The address terminal 13 is a terminal to which address signals A0 to A15and BA0 to BA2 are supplied, and the supplied address signals A0 to A15and BA0 to BA2 are supplied to an address input buffer 41 provided inthe interface chip IF. An output of the address input buffer 41 iscommonly supplied to the core chips CC0 to CC7 through the throughsilicon vias TSV. The address input buffer 41 takes in respectively fromoutside the address signals A0 to A15 and BA0 to BA2 that are suppliedfrom outside of the semiconductor memory device 10, and holds(determines) the signals, based on control of the command input buffer31. This corresponds to edges of the external clock signals CK and /CKrelevant to the clock generation circuit. That is, the address inputbuffer 41 included in the interface chip IF operates to satisfy asetting up and holding time of a so-called supplied-input signal basedon the edges of the external clock signals CK and /CK, which arenecessary to communicate outside of the semiconductor memory device 10.The address input buffer 41 supplies the address signals determined viaa through silicon via TSV to the input buffer B1 via a relevant throughsilicon via TSV. The address signals A0 to A15 are supplied to a moderegister 42 provided in the interface chip IF, when the semiconductormemory device 10 enters a mode register set. The mode register 42 is setin advance with the whole operation modes or the like of thesemiconductor memory device 10. When the semiconductor memory device 10is set in the first operation mode, the mode selection signal PRAbecomes at a high level. When the semiconductor memory device 10 is setin the second operation mode, the mode selection signal PRA becomes at alow level. As shown in FIG. 4, the mode selection signal PRA is suppliedto the refresh-control-signal generation circuit 100. The addresssignals BA0 to BA2 (bank addresses) are decoded by an address decoder(not shown in the drawings) provided in the interface chip IF, and abank selection signal B that is obtained by the decoding is supplied toa data latch circuit 25. This is because bank selection of the writedata is performed in the interface chip IF. Among the address signals A0to A15, three bits of the address signals A13, A14, and A15 areinformation for selecting the core chips CC0 to CC7, and areoccasionally referred to as address information SIDADD.

The data input/output terminal 14 is used to input/output read data orwrite data DQ0 to DQ15 relevant to external access. The data strobeterminals 15 a and 15 b are terminals that are used to input/outputstrobe signals DQS and /DQS. The data input/output terminal 14 and thedata strobe terminals 15 a and 15 b are connected to the input/outputbuffer circuit 23 provided in the interface chip IF. The input/outputbuffer circuit 23 includes an input buffer IB and an output buffer OB,and inputs/outputs the read data or the write data DQ0 to DQ15 and thestrobe signals DQS and /DQS in synchronization with the input/outputclock signal LCLK supplied from the DLL circuit 22. If an internalon-die termination signal IODT is supplied from the command decoder 32,the input/output buffer circuit 23 causes the output buffer OB tofunction as a termination resistor. An impedance code DRZQ is suppliedfrom the calibration circuit 24 to the input/output buffer circuit 23.Thereby, impedance of the output buffer OB is designated. Theinput/output buffer circuit 23 includes a well-known FIFO circuit.

The calibration circuit 24 includes a replica buffer RB that has thesame circuit configuration as the output buffer OB. If the calibrationsignal ZQ is supplied from the command decoder 32, the calibrationcircuit 24 refers to a resistance value of an external resistor (notshown in the drawings) connected to the calibration terminal 16 andperforms a calibration operation. The calibration operation matches theimpedance of the replica buffer RB with the resistance value of theexternal resistor, and supplies the obtained impedance code DRZQ to theinput/output buffer circuit 23. Thereby, the impedance of the outputbuffer OB is adjusted to a desired value.

The input/output buffer circuit 23 is connected to a data latch circuit25. The data latch circuit 25 includes a FIFO circuit (not shown in thedrawings) that realizes a FIFO function which operates by latencycontrol realizing the well-known DDR function and a multiplexer MUX (notshown in the drawings). The input/output buffer circuit 23 convertsparallel read data, which is supplied from the core chips CC0 to CC7,into serial read data, and converts serial write data, which is suppliedfrom the input/output buffer, into parallel write data. Accordingly, thedata latch circuit 25 and the input/output buffer circuit 23 areconnected in serial and the data latch circuit 25 and the core chips CC0to CC7 are connected in parallel. In this embodiment, each of the corechips CC0 to CC7 is the back end unit of the DDR3-type SDRAM and aprefetch number is 8 bits. The data latch circuit 25 and each banks ofthe core chips CC0 to CC7 are connected respectively, and the number ofbanks that are included in each of the core chips CC0 to CC7 is 8.Accordingly, connection of the data latch circuit and the core chips CC0to CC7 becomes 64 bits (8 bits×8 banks) for each DQ.

Parallel data, not converted into serial data, is basically transferredbetween the data latch circuit 25 and the core chips CC0 to CC7. Thatis, in a common SDRAM (in the SDRAM, a front end unit and a back endunit are constructed in one chip), between the outside of the chip andthe SDRAM, data is input/output in serial (that is, the number of datainput/output terminals is one for each DQ). However, in the core chipsCC0 to CC7, an input/output of data between the interface chip IF andthe core chips is performed in parallel. This point is the importantdifference between the common SDRAM and the core chips CC0 to CC7.However, all of the prefetched parallel data do not need to beinput/output using the different through silicon vias TSV, and partialparallel/serial conversion may be performed in the core chips CC0 to CC7and the number of through silicon vias TSV that are needed for each DQmay be reduced. For example, all of data of 64 bits for each DQ do notneed to be input/output using the different through silicon vias TSV,and 2-bit parallel/serial conversion may be performed in the core chipsCC0 to CC7 and the number of through silicon vias TSV that are neededfor each DQ may be reduced to ½ (32).

A function for enabling a test in an interface chip unit is added to thedata latch circuit 25. The interface chip IF does not have the back endunit. For this reason, the interface chip cannot be operated as a singlechip in principle. However, if the interface chip never operates as thesingle chip, an operation test of the interface chip in a wafer statemay not be performed. This means that the semiconductor memory device 10cannot be tested in case an assembly process of the interface chip andthe plural core chips is not executed, and the interface chip is testedby testing the semiconductor memory device 10. In this case, when adefect, which cannot be recovered, exists in the interface chip, theentire semiconductor memory device is not available. In consideration ofthis point, in this embodiment, a portion of a pseudo back end unit fora test is provided in the data latch circuit 25, and a simple memoryfunction is enabled at the time of a test.

The power supply terminals 17 a and 17 b are terminals to which powersupply potentials VDD and VSS are supplied, respectively. The powersupply terminals 17 a and 17 b are connected to a power-on detectingcircuit 43 provided in the interface chip IF and are also connected tothe core chips CC0 to CC7 through the through silicon vias TSV. Thepower-on detecting circuit 43 detects the supply of power. On detectingthe supply of power, the power-on detecting circuit 43 activates a layeraddress control circuit 45 on the interface chip IF.

The layer address control circuit 45 changes a layer address due to theI/O configuration of the semiconductor device 10 according to thepresent embodiment. As described above, the semiconductor memory device10 includes 16 data input/output terminals 14. Thereby, a maximum I/Onumber can be set to 16 bits (DQ0 to DQ15). However, the I/O number isnot fixed to 16 bits and may be set to 8 bits (DQ0 to DQ7) or 4 bits(DQ0 to DQ3). The address allocation is changed according to the I/Onumber and the layer address is also changed. The layer address controlcircuit 45 changes the address allocation according to the I/O numberand is commonly connected to the core chips CC0 to CC7 through thethrough silicon vias TSV.

The interface chip IF is also provided with a layer address settingcircuit 44. The layer address setting circuit 44 is connected to thecore chips CC0 to CC7 through the through silicon vias TSV. The layeraddress setting circuit 44 is cascade-connected to the layer addressgenerating circuit 46 of the core chips CC0 to CC7 using the throughsilicon via TSV2 of the type shown in FIG. 2B, and reads out the layeraddresses set to the core chips CC0 to CC7 at testing.

The interface chip IF is also provided with a defective chip informationholding circuit 33. When a defective core chip, which does not operatenormally, is discovered after an assembly, the defective chipinformation holding circuit 33 holds its chip number. The defective chipinformation holding circuit 33 is connected to the core chips CC0 to CC7through the through silicon vias TSV. The defective chip informationholding circuit 33 is connected to the core chips CC0 to CC7 while beingshifted, using the through silicon via TSV3 of the type shown in FIG.2C.

The above description is the outline of the connection relationshipbetween the external terminals and the interface chip IF and the circuitconfiguration of the interface chip IF. Next, the circuit configurationof the core chips CC0 to CC7 will be described.

As shown in FIG. 4, memory cell arrays 50 that are included in the corechips CC0 to CC7 performing the back end function are divided into eightbanks. These banks are a unit that can individually receive a command.In other words, the banks are independent regions that can mutuallyindependently operate based on non-exclusive control. Each back can beindependently accessed from the outside of the semiconductor memorydevice 10. For example, a part of the memory cell array 50 belonging tothe bank 1 and another part of the memory cell array 50 belonging to thebank 2 are controlled nonexclusively. That is, word lines WL and bitlines BL corresponding to each banks respectively are independentlyaccessed at same period by different commands one another. For example,while the bank 1 is maintained to be active (the word lines and the bitlines are controlled to be active), the bank 2 can be controlled to beactive. However, the external terminals (for example, plural controlterminals and plural I/O terminals) of the semiconductor memory device10 are shared. Therefore, data in the bank 1 and data in the bank 2 areinput to and output from external terminals of the semiconductor memorydevice via I/O terminals at mutually different times in a time axis. Ineach of the memory cell arrays 50, the plural word lines WL and theplural bit lines BL intersect each other, and memory cells MC aredisposed at intersections thereof (in FIG. 4, only one word line WL, onebit line BL, and one memory cell MC are shown). The word line WL isselected by a row decoder 51. The bit line BL is connected to acorresponding sense amplifier SA in a sense circuit 53. The senseamplifier SA is selected by a column decoder 52. Because the memory cellMC is a DRAM cell, a data holding operation is necessary at eachpredetermined time by a refresh operation.

Because the semiconductor memory device 10 according to the presentembodiment includes eight core chips, there are 64 banks in total.However, from outside of the semiconductor memory device such as amemory controller, as shown in FIG. 5, banks 0 of the core chips CC0 toCC7 are collectively recognized as one bank, and similarly, banks 1 ofthe core chips CC0 to CC7 are collectively recognized as one bank, banksof the core chips CC0 to CC7 are collectively recognized as one bank,and so on. Therefore, the memory controller recognizes that a DRAMincludes eight banks. By setting each bank of the core chips CC0 to CC7as an independent region, plural independent regions in which theindependent regions are collected as one by crossing the core chips CC0to CC7 are occasionally referred to as one memory bank.

The row decoder 51 is controlled by a row address supplied from a rowcontrol circuit 61. The row control circuit 61 includes an addressbuffer 61 a that receives a row address supplied from the interface chipIF through the through silicon via TSV, and the row address that isbuffered by the address buffer 61 a is supplied to the row decoder 51.The address signal that is supplied through the through silicon via TSVis supplied to the row control circuit 61 through the input buffer B1.Further, the row control circuit 61 also includes a refresh counter 61b, and when a refresh-control-signal dividing circuit 300 issues arefresh control signal REFd, a bank address and a row address indicatedby the refresh counter 61 b is supplied to the row decoder 51 in placeof the address signal that supplies via the through silicon via TSV. Therefresh control signal REFd is generated via the refresh control signalREFb that is supplied from the interface chip IF to the control logiccircuit 63 of the core chip via the through silicon via TSV, and via arefresh control signal REFc that is supplied to therefresh-control-signal dividing circuit 300 from the control logiccircuit 63. This configuration is described in detail later.

The column decoder 52 is controlled by a column address supplied from acolumn control circuit 62. The column control circuit 62 includes anaddress buffer 62 a that receives the column address supplied from theinterface chip IF through the through silicon via TSV, and the columnaddress that is buffered by the address buffer 62 a is supplied to thecolumn decoder 52. The column control circuit 62 also includes a burstcounter 62 b that counts the burst length.

The sense amplifier SA selected by the column decoder 52 is connected tothe data control circuit 54 through some amplifiers (sub-amplifiers ordata amplifiers or the like) which are not shown in the drawings.Thereby, read data of 8 bits (=prefetch number) for each I/O (DQ) isoutput from the data control circuit 54 at reading, and write data of 8bits is input to the data control circuit 54 at writing. The datacontrol circuit 54 and the interface chip IF are connected in parallelthrough the through silicon via TSV.

The control logic circuit 63 receives an internal command ICMD suppliedfrom the interface chip IF through the through silicon via TSV andcontrols the row control circuit 61 and the column control circuit 62 inthe core chip, based on the internal command ICMD. The control logiccircuit 63 is connected to a layer address comparing circuit(determining circuit) 47. The layer address comparison circuit 47detects whether a corresponding core chip is to be accessed, and thelayer address comparison circuit 47 performs the detection by comparingthe address information SIDADD as a part of an address signal suppliedfrom the interface IF via the through silicon via TSV with a layeraddress SID (chip identification information) that is set in thelayer-address generation circuit 46. The layer address SID is a signalhaving been determined by a predetermined operation within thesemiconductor memory device before a command of read, write, or refreshis supplied to the semiconductor memory device from outside.

The control logic circuit 63 includes a refresh control circuit 200.Although details thereof are described later, the refresh controlcircuit 200 directly outputs as the refresh control signal REFc for onetime the refresh control signal REFb for one time that is supplied fromthe interface IF when the first operation mode is selected. When thesecond operation mode is selected, the refresh control circuit 200counts the refresh control signal REFb that is supplied for plural timesfrom the interface chip IF, and functions to activate the refreshcontrol signal REFc when a predetermined count value is obtained. Anoperation mode is assigned by the mode selection signal PRA that issupplied from a mode register 64. The refresh control signal REFc issupplied to the refresh-control-signal dividing circuit 300. Therefresh-control-signal dividing circuit 300 activates the refreshcontrol signal REFd for plural times when the refresh control signalREFc is activated for one time. The refresh control signal REFd issupplied to the refresh counter 61 b within the row control circuit 61,and causes to refresh the bank address and the row address indicated bythe refresh counter 61 b. It suffices that there is at least any one ofthe mode register 64 included in each of the core chips CC0 to CC7 andthe mode register 42 included in the interface chip IF, within thesemiconductor memory device 10. In this case, the mode selection signalPRA is supplied to another chip via the through silicon via TSV from achip in which a mode register is arranged.

In the layer address generating circuit 46, unique layer addresses areset to the core chips CC0 to CC7, respectively, at initialization of thesemiconductor memory device. A method of setting the layer addresses isas follows. First, after the semiconductor memory device 10 isinitialized, a minimum value (0, 0, 0) as an initial value is set to thelayer address generating circuits 46 of the core chips CC0 to CC7. Thelayer address generating circuits 46 of the core chips CC0 to CC7 arecascade-connected using the through silicon vias TSV of the type shownin FIG. 2B, and have increment circuits provided therein. The layeraddress (0, 0, 0) that is set to the layer address generating circuit 46of the core chip CC0 of the uppermost layer is transmitted to the layeraddress generating circuit 46 of the second core chip CC1 through thethrough silicon via TSV and is incremented. As a result, a differentlayer address (0, 0, 1) is generated. Hereinafter, in the same way asthe above case, the generated layer addresses are transmitted to thecore chips of the lower layers and the layer address generating circuits46 in the core chips increment the transmitted layer addresses. A layeraddress having a maximum value (1, 1, 1) is set to the layer addressgenerating circuit 46 of the core chip CC7 of the lowermost layer.Thereby, the unique layer addresses are set to the core chips CC0 toCC7, respectively.

The layer address generating circuit 46 is provided with a defectivechip signal DEF supplied from the defective chip information holdingcircuit 33 of the interface chip IF, through the through silicon viaTSV. As the defective chip signal DEF is supplied to the individual corechips CC0 to CC7 using the through silicon via TSV3 of the type shown inFIG. 2C, the defective chip signals DEF can be supplied to the corechips CC0 to CC7, individually. The defective chip signal DEF isactivated when the corresponding core chip is a defective chip. Thelayer address generating circuit 46 transmits a non-incremented layeraddress, not an incremented layer address, to the core chip of the lowerlayer when the defective chip signal DEF is activated. The defectivechip signal DEF is also supplied to the control logic circuit 63. Whenthe defective chip signal DEF is activated, the control logic circuit 63is completely halted. Thereby, the defective core chip performs neitherread operation nor write operation, even though an address signal or acommand signal is input from the interface chip IF.

An output of the control logic circuit 63 is also supplied to a moderegister 64. When an output of the control logic circuit 63 shows a moderegister set, the mode register 64 is updated by an address signal.Thereby, operation modes of the core chips CC0 to CC7 are set.

Each of the core chips CC0 to CC7 has an internal voltage generatingcircuit 70. The internal voltage generating circuit 70 is provided withpower supply potentials VDD and VSS. The internal voltage generatingcircuit 70 receives these power supply potentials and generates variousinternal voltages. As the internal voltages that are generated by theinternal voltage generating circuit 70, an internal voltage VPERI (≈VDD)for operation power of various peripheral circuits, an internal voltageVARY (<VDD) for an array voltage of the memory cell array 50, and aninternal voltage VPP (>VDD) for an activation potential of the word lineWL are included. In each of the core chips CC0 to CC7, a power-ondetecting circuit 71 is also provided. When the supply of power isdetected, the power-on detecting circuit 71 resets various internalcircuits.

The peripheral circuits in the core chips CC0 to CC7 operates insynchronization with the internal clock signal ICLK that is suppliedform the interface chip IF through the through silicon via TSV. Theinternal clock signal ICLK supplied through the through silicon via TSVis supplied to the various peripheral circuits through the input bufferB2.

The above description is the basic circuit configuration of the corechips CC0 to CC7. In the core chips CC0 to CC7, the front end unit foran interface with the external device is not provided. Therefore thecore chip cannot operate as a single chip in principle. However, if thecore chip never operates as the single chip, an operation test of thecore chip in a wafer state may not be performed. This means that thesemiconductor memory device 10 cannot be tested, before the interfacechip and the plural core chips are fully assembled. In other words, theindividual core chips are tested when testing the semiconductor memorydevice 10. When unrecoverable defect exists in the core chips, theentire semiconductor memory device 10 is led to be unavailable. In thisembodiment, in the core chips CC0 to CC7, a portion of a pseudo frontend unit, for testing, that includes some test pads TP and a test frontend unit of a test command decoder 65 is provided, and an address signaland test data or a command signal can be input from the test pads TP. Itis noted that the test front end unit is provided for a simple test in awafer test, and does not have all of the front end functions in theinterface chip. For example, since an operation frequency of the corechips is lower than an operation frequency of the front end unit, thetest front end unit can be simply realized with a circuit that performsa test with a low frequency.

Kinds of the test pads TP are almost the same as those of the externalterminals provided in the interposer IP. Specifically, the test padsinclude a test pad TP1 to which a clock signal is input, a test pad TP2to which an address signal is input, a test pad TP3 to which a commandsignal is input, a test pad TP4 for input/output test data, a test padTP5 for input/output a data strobe signal, and a test pad TP6 for apower supply potential.

A common external command (not decoded) is input at testing. Therefore,the test command decoder 65 is also provided in each of the core chipsCC0 to CC7. Because serial test data is input and output at testing, atest input/output circuit 55 is also provided in each of the core chipsCC0 to CC7.

This is the entire configuration of the semiconductor memory device 10.Because in the semiconductor memory device 10, the 8 core chips of 1 Gbare laminated, the semiconductor memory device 10 has a memory capacityof 8 Gb in total. Because the chip selection signal /CS is input to oneterminal (chip selection terminal), the semiconductor memory device isrecognized as a single DRAM having the memory capacity of 8 Gb, in viewof the controller.

FIG. 6 shows an extract of circuits relevant to generation of a layeraddress.

As shown in FIG. 6, the layer-address generation circuit 46 is providedin each of the core chips CC0 to CC7, and these layer-address generationcircuits 46 are connected in cascade via the through silicon via TSV2 ofthe type shown in FIG. 2B. Each layer-address generation circuit 46includes a layer address register 46 a, an increment circuit 46 b, and atransfer circuit 46 c.

The layer address register 46 a holds a layer address (chipidentification information) SID of three bits. When the power-ondetection circuit 71 shown in FIG. 4 detects an input of a power source,this value is initialized to a minimum value (0, 0, 0). In the core chipCC0 of a top layer, a value (0, 0, 1) obtained by the increment circuit46 b by incrementing a layer address SID (0, 0, 0) set in the layeraddress register 46 a is generated. The transfer circuit 46 c transfersthe layer address SID (0, 0, 1) of the incremented value to the corechip CC1 of a lower layer. The transferred layer address SID (0, 0, 1)is set in the layer address register 46 a of the core chip CC1.

In the core chip CC1, a value (0, 1, 0) obtained by the incrementcircuit 46 b by incrementing the layer address SID (0, 0, 1) set in thelayer address register 46 a is generated. The transfer circuit 46 ctransfers a layer address SID (0, 1, 0) of the incremented values to thecore chip CC2 of a lower layer.

Thereafter, similarly, incremented layer addresses SID are sequentiallytransferred to core chips of lower layers. Finally, a maximum value (1,1, 1) is set as a layer address SID in the layer address register 46 aof the core chip CC7 of the lowest layer. With this configuration,specific layer addresses SID are set in the core chips CC0 to CC7,respectively.

The defective-chip signal DEF is supplied to the layer-addressgeneration circuit 46 from the defective-chip-information holdingcircuit 33 of the interface chip IF via the through silicon via TSV3 ofthe type shown in FIG. 2C. The defective-chip signal DEF is a signalhaving eight bits, and each bit is supplied to a corresponding one ofthe core chips CC0 to CC7. A core chip of which a bit corresponding tothe defective-chip signal DEF is active is a defective chip. In the corechip of which a bit corresponding to the defective-chip signal DEF isactive, the transfer circuit 46 c transfers a non-incremented layeraddress SID, not an incremented layer address SID, to a core chip of alower layer. Accordingly, the defective chip is skipped when allocatinga layer address SID. That is, a layer address SID that is allocated toeach of the core chips CC0 to CC7 is not fixed, but is variabledepending on the defective-chip signal DEF. Although a layer address SIDthat is the same as that of a core chip of a lower layer is allocated toa defective chip, activation of the control logic circuit 63 isprohibited in the defective chip. Therefore, a read operation or a writeoperation is not actually performed even when an address signal or acommand signal is input to the defective chip from the interface chipIF.

A layer address SID having been set as described above is supplied tothe layer address comparison circuit 47 within the same core chip amongthe core chips CC0 to CC7. The layer address comparison circuitconstitutes “determining circuit” that determines whether the addressinformation SIDADD that is supplied from the interface chip IF assignsthe self-core chip. The layer address comparison circuit 47 compares thelayer address SID that is supplied from the layer-address generationcircuit 46 with the address information SIDADD as a part of the addresssignal that is supplied from the interface chip IF via the throughsilicon via TSV. When the layer address SID and the address informationSIDADD match each other, the layer address comparison circuit 47activates an enable signal SIDEN. The address information SIDADD ishigh-order three bits (A13, A14, and A15) of the address signal. Becausethe address information SIDADD is supplied in common to the core chipsCC0 to CC7 via the through silicon via TSV1 of the type shown in FIG.2A, only one core chip is detected to match by the layer addresscomparison circuit 47 in the semiconductor memory device 10. When thelayer address comparison circuit 47 detects a match, a corresponding oneof the control logic circuits 63 is activated, and the internal commandICMD supplied from the interface chip IF becomes valid.

SID0 and SID1 as low-order two bits of the layer address SID are alsodirectly supplied to the refresh control circuit 200 within the controllogic circuit 63. The mode selection signal PRA is also supplied to therefresh control circuit 200. Accordingly, when the refresh controlsignal REFb is supplied from the interface chip IF, the refresh controlcircuit 200 generates the refresh control signal REFc based on theenable signal SIDEN when the first operation mode is selected by themode selection signal PRA. On the other hand, when the second operationmode is selected by the mode selection signal PRA, the refresh controlcircuit 200 generates the refresh control signal REFc based on SID0 andSID1 as low-order two bits of the layer address SID.

FIG. 7 is a circuit diagram of the refresh-control-signal generationcircuit 100 included in the interface chip IF.

As shown in FIG. 7, the refresh-control-signal generation circuit 100includes a counter circuit 110, a state circuit 120, a delay circuit130, and an SR latch circuit 140. An output of a NAND gate circuit 141that receives the internal refresh command REFa and an inversion signalof the mode selection signal PRA is supplied to a set input terminal (S)of the SR latch circuit 140. Therefore, when the mode selection signalPRA is at a high level (the first operation mode), setting of the SRlatch circuit 140 is prohibited. On the other hand, when the modeselection signal PRA is at a low level (the second operation mode), theSR latch circuit 140 is set in response to activation of the internalrefresh command REFa.

An output of the SR latch circuit 140 is supplied to a one-shot-pulsegeneration circuit 142 and to a complex gate circuit 143. An internalsignal RREFT as an output of the complex gate circuit 143 is input,together with a count signal CT as an output of a counter circuit 110,to an AND gate circuit 144. An output of the AND gate circuit 144 isinput, together with the internal refresh command REFa, to an OR gatecircuit 145. An output of the OR gate circuit 145 is used as the refreshcontrol signal REFb.

FIG. 8 is a circuit diagram of the counter circuit 110.

As shown in FIG. 8, the counter circuit 110 includes two flip-flopcircuits 111 and 112, and a NAND gate circuit 113 that receives outputbits C0 and C1 of the flip-flop circuits 111 and 112. The internalsignal RREFT is input to clock input terminals of the flip-flop circuits111 and 112. Because the two flip-flop circuits 111 and 112 areconnected in cascade as shown in FIG. 8, these circuits constitute a2-bit binary counter. That is, as shown in FIG. 9, the output bit C0 ofthe flip-flop circuit 111 is inverted each time when the internal signalRREFT is activated, and the output bit C1 of the flip-flop circuit 112is inverted each time when the internal signal RREFT is activated fortwo times. Therefore, the count signal CT that is at a low level at aninitial state becomes at a high level in response to activation of theinternal signal RREFT, and returns to a low level in response to thefourth activation of the internal signal RREFT. The count values C0 andC1 of the counter circuit 110 are reset to C0, C1=(0, 0) in response toa reset signal Reset.

As shown in FIG. 7, the internal signal RREFT is also supplied to thestate circuit 120 and to the delay circuit 130. The state circuit 120sets a refresh state signal PMCBAT at a high level during a constantperiod after the internal signal RREFT is activated. The refresh statesignal PMCBAT shows a refresh period, and is supplied to a reset inputterminal (R) of the SR latch circuit 140. The delay circuit 130generates a delay signal RE that is obtained by delaying the internalsignal RREFT. The delay signal RE is supplied to the complex gatecircuit 143.

FIGS. 10 and 11 are timing diagrams for explaining operations of therefresh-control-signal generation circuit 100, where FIG. 10 shows anoperation when the first operation mode is selected and FIG. 11 shows anoperation when the second operation mode is selected.

As described above, the refresh-control-signal generation circuit 100included in the interface chip IF fixes the internal signal RREFT at alow level as shown in FIG. 10 because the SR latch circuit 140 is notset in the first operation mode in which the mode selection signal PRAis at a high level. Therefore, only the refresh control signal REFb isgenerated for one time in response to the internal refresh command REFafor one time, and the counter circuit 110 does not perform a countoperation.

On the other hand, in the second operation mode in which the modeselection signal PRA is at a low level, the SR latch circuit 140 is setin response to the internal refresh command REFa for one time, andtherefore the internal signal RREFT is activated, as shown in FIG. 11.This internal signal RREFT is input to the delay circuit 130, and is fedback to the complex gate circuit 143 as the delay signal RE. Therefore,the internal signal RREFT is activated for plural times in apredetermined cycle. The internal signal RREFT is output as the refreshcontrol signal REFb via the AND gate circuit 144 and the OR gate circuit145. Therefore, the refresh control signal REFb is also activated in apredetermined cycle.

The counter circuit 110 counts the number of times of activating theinternal signal RREFT, and the count signal CT changes to a low level ata fourth count. Accordingly, activation of the refresh control signalREFb based on the internal signal RREFT is prohibited. Thereafter, therefresh state signal PMCBAT changes to a low level, and the SR latchcircuit 140 is reset.

As explained above, in the second operation mode, therefresh-control-signal generation circuit 100 included in the interfacechip IF activates the refresh control signal REFb for four times inresponse to the internal refresh command REFa for one time. Out ofactivation for four times, the first activation is based on passing ofthe internal refresh command REFa through the OR gate circuit 145, andthe second to fourth activation is automatically made by the complexgate circuit 143 and the delay circuit 130 that are connected in a loopshape.

FIG. 12 is a circuit diagram of the refresh control circuit 200 includedin each of the core chips CC0 to CC7.

As shown in FIG. 12, the refresh control circuit 200 includes a countercircuit 210 that counts the refresh control signal REFb supplied fromthe interface chip IF, and a comparison circuit 220 that compares outputbits C0 and C1 of the counter circuit 210 with low-order two bits (SID0and SID1) of the layer address SID, respectively.

The counter circuit 210 is a 2-bit binary counter consisting of twoflip-flop circuits 211 and 212 that are connected in cascade. Therefresh control signal REFb is input to a clock input terminal of eachof these flip-flop circuits. Therefore, the output bit C0 of theflip-flop circuit 211 is inverted each time when the refresh controlsignal REFb is activated, and the output bit C1 of the flip-flop circuit212 is inverted each time when the refresh control signal REFb isactivated for two times. Count values C0 and C1 of the counter circuit210 are set to arbitrary values such as C0, C1=(0, 0), for example, inresponse to a set signal Set.

The comparison circuit 220 compares two bits of the count values C0 andC1 with the low-order two bits (SID1 and SID1) of the layer address SID,respectively. When all of the respective bits match each other, thecomparison circuit 220 activates an enable signal REFEN via a complexgate circuit 230. The enable signal REFEN and the refresh control signalREFb are input to an AND gate circuit 231 having three inputs. An outputof the AND gate circuit 231 is used as the refresh control signal REFc.

An enable signal SIDENa is input to a remaining input of the AND gatecircuit 231. The enable signal SIDENa is supplied from an OR gatecircuit 232. The enable signal SIDEN and an inversion signal of the modeselection signal PRA are supplied to the OR gate circuit 232. The modeselection signal PRA is also supplied to the complex gate circuit 230.Accordingly, when the mode selection signal PRA is at a high level (thefirst operation mode), the enable signal REFEN is activated at a highlevel regardless of an operation of the comparison circuit 220, andmeanwhile, a logic level of the enable signal SIDENa matches a logiclevel of the enable signal SIDEN. On the other hand, when the modeselection signal PRA is at a low level (the second operation mode), theenable signal SIDENa is activated at a high level regardless of anoperation of the layer address comparison circuit 47, and meanwhile, theenable signal REFEN is activated at a high level only when thecomparison circuit 220 detects a match.

FIGS. 13 and 14 are timing diagrams for explaining an operation of therefresh control circuit 200 included in each of the core chips CC0 toCC7, where FIG. 13 shows an operation when the first operation mode isselected and FIG. 14 shows an operation when the second operation modeis selected.

As shown in FIG. 13, the refresh control circuit 200 included in each ofthe core chips CC0 to CC7 activates the enable signal REFEN at a highlevel regardless of an operation of the comparison circuit 220 in thefirst operation mode in which the mode selection signal PRA is at a highlevel. On the other hand, a logic level of the enable signal SIDENamatches a logic level of the enable signal SIDEN. Therefore, the refreshcontrol circuit 200 included in each of the core chips CC0 to CC7activates the refresh control signal REFc for one time in response tothe refresh control signal REFb for one time in a condition that thelayer address comparison circuit 47 detects a match.

On the other hand, in the second operation mode in which the modeselection signal PRA is at a low level, the enable signal SIDENa isfixed at a high level as shown in FIG. 14. Meanwhile, because the enablesignal REFEN is activated only when the comparison circuit 220 detects amatch, the refresh control signal REFc in each of the core chips CC0 toCC7 is activated for one time each time when the refresh control signalREFb supplied from the interface chip IF is activated for four times. Inan example shown in FIG. 14, an output of the refresh control circuit200 of each of the core chips CC2 and CC6 is shown. Low-order two bitsSID0 and SID1 of the layer address SID are equal to 1 and 0 (theseindicate two core chips CC2 and CC6). Therefore, the refresh controlsignal REFc is activated when the refresh control signal REFb isactivated when count values of the counter circuit 210 are C0, C1=1, 0.That is, the core chips CC2 and CC6 are refreshed in response to thethird activation of the refresh control signal REFb out of activation ofthe refresh control signal REFb for four times. Similarly, the refreshcontrol circuit 200 of each of the core chips CC0 and CC4 generates therefresh control signal REFc in response to the first activation of therefresh control signal REFb out of activation of the refresh controlsignal REFb for four times. The refresh control circuit 200 of each ofthe core chips CC1 and CC5 generates the refresh control signal REFc inresponse to the second activation of the refresh control signal REFb outof activation of the refresh control signal REFb for four times. Therefresh control circuit 200 of each of the core chips CC3 and CC7generates the refresh control signal REFc in response to the fourthactivation of the refresh control signal REFb out of activation of therefresh control signal REFb for four times. These generations are shownin FIG. 19.

FIG. 15 is a timing diagram for explaining an operation of therefresh-control-signal dividing circuit 300 included in each of the corechips CC0 to CC7.

As shown in FIG. 15, the refresh-control-signal dividing circuit 300generates in time series the refresh control signal REFd for four timesin response to the refresh control signal REFc for one time. The refreshcontrol signal REFd is supplied to the refresh counter 61 b shown inFIG. 4.

FIG. 16 is a circuit diagram of the refresh counter 61 b included ineach of the core chips CC0 to CC7.

As shown in FIG. 16, the refresh counter 61 b includes plural count bitcircuits CB each of which includes two latch circuits LT0 and LT1 thatare connected circularly via an inverter INV. An output of each countbit circuit is used as a clock of a next-stage count bit circuit. Therefresh control signal REFd is used in a clock of a first-stage countbit circuit. Based on this configuration, the refresh counter 61 bfunctions as a binary counter that counts the refresh control signalREFd. Low-order two bits of the count value are used as a bank addressBADD, and other high-order bits are used as a row address XADD.

FIG. 17 is a timing diagram for explaining an operation of the refreshcounter 61 b included in each of the core chips CC0 to CC7.

As shown in FIG. 17, a value of the bank address BADD is incrementedeach time when the refresh control signal REFd is activated.Accordingly, the bank address BADD makes a circuit corresponding to theactivation of the refresh control signal REFd for four times. When thebank address BADD makes the circuit, a row address XADD as a high-orderbit of the bank address BADD is incremented. As already explained, therefresh control signal REFd is generated continuously for four timeseach time when the refresh control signal REFc is activated for onetime. Therefore, when the refresh control signal REFc is activated forone time, four bank addresses BADD relevant to one row address XADD aregenerated. As a result, when the refresh control signal REFc isactivated for one time, one row address XADD and four bank addressesBADD relevant to the one row address XADD are given to plural rowdecoders 51 corresponding to the banks shown in FIG. 4.

Because one core chip includes eight banks 0 to 7, two banks aresimultaneously selected corresponding to the refresh control signal REFdfor one time by a 2-bit bank address BADD that is output from therefresh counter 61 b. Specifically, when the bank address BADD is equalto 00, the bank 0 and the bank 4 are selected. When the bank addressBADD is equal to 01, the bank 1 and the bank 5 are selected. When thebank address BADD is equal to 10, the bank 2 and the bank 6 areselected. When the bank address BADD is equal to 11, the bank 3 and thebank 7 are selected. Therefore, the refresh-control-signal dividingcircuit 300 performs a refresh operation in the order of the banks 0 and4, the banks 1 and 5, the banks 2 and 6, the banks 3 and 7 by therefresh control signal REFd for four times generated in chronologicalorder corresponding to the refresh control signal REFc for one time. Asimultaneous selection of two banks also includes that the memory cellarrays 50 relevant to the two banks respectively access simultaneouslyor that operation currents of the memory cell arrays 50 relevant to thetwo banks respectively are delayed so as to be slightly shifted eachother. For example, the simultaneous selection of two banks includes adelaying of slightly shifting the operation currents of the sensecircuits 53 relevant to the two banks respectively corresponding to therefresh control signal REFd for one time. These operations are valid toreduce noise within the semiconductor memory device 10.

FIG. 18 is a timing diagram for explaining an operation of thesemiconductor memory device 10 when the first operation mode isselected.

In an example shown in FIG. 18, at a time to, a refresh command REF forone time and the address information SIDADD (first address information)for assigning the core chip CC0 relevant to the refresh command REF forone time are input from outside. In response to the input, the refreshcontrol signal REFb is activated for one time, and this activated signalis supplied to all the core chips CC0 to CC7. However, when the firstoperation mode is selected, only a core chip assigned by the addressinformation SIDADD becomes valid. Therefore, the refresh control signalREFc is activated for one time in the core chip CC0, and meanwhile, therefresh control signal REFc is not activated in other core chips CC1 toCC7. Consequently, the core chip CC0 is refreshed at an addressindicated by the refresh counter 61 b included in the core chip CC0 inonly the core chip CC0. Banks of the core chip CC0 are refresheddispersedly in the order of the banks 0 and 4, the banks 1 and 5, thebanks 2 and 6, the banks 3 and 7 by the refresh control signal REFd forfour times in time series as described above. Therefore, a peak ofcurrent consumption can be suppressed.

As described above, in the first operation mode, only a specific corechip can perform a refresh operation in response to the refresh commandREF for one time and the address information SIDADD for assigning thecore chip CC0 relevant to the refresh command REF for one time that areinput from outside. Therefore, other core chips become in an idle statefrom a viewpoint of outside of the semiconductor memory device.Consequently, in the middle of a refresh operation (refresh access) thatis performed by a certain core chip, an access (external access) to amemory cell included in other core chip becomes possible. In the exampleshown in FIG. 18, at a time t1, an active command ACT for one time andthe address information SIDADD (second address information) forassigning the core chip CC2 relevant to the active command ACT for onetime are input from outside.

Accordingly, an active control signal IACT as a type of the internalcommand ICMD of the interface IF is activated, and this activated signalis supplied to all the core chips CC0 to CC7. However, because the corechip CC2 is selected by the address information SIDADD, the activecontrol signal IACT becomes valid in only the core chip CC2. The corechip CC2 performs an operation relevant to the active command ACTcorresponding to the active control signal IACT.

Further, in the example shown in FIG. 18, at a time t2, the refreshcommand REF for one time and the address information SIDADD (the firstaddress information) for assigning the core chip CC1 relevant to therefresh command REF for one time are input from outside. At the time t2,the core chip CC2 is in the middle of an access (in the middle of anexternal access in a non-idle state). However, because the addressinformation SIDADD assigns the core chip CC1 that is different from thecore chip CC2, the semiconductor memory device 10 can accept the refreshcommand REF at the time t2. At a time t3, the core chip CC2 is in themiddle of an access (in the middle of an external access in a non-idlestate). However, because the address information SIDADD assigns the corechip CC3 that is different from the core chip CC2, the semiconductormemory device 10 can accept the active command ACT at the time t3.

As described above, when the first operation mode is selected, thesemiconductor memory device 10 can perform a refresh operation byselecting a specific core chip. Consequently, in the middle of a refreshoperation that is performed by a certain core chip, an access to amemory cell included in other core chip becomes possible. Conversely, inthe middle of an access operation that is performed by a certain corechip, a refresh operation can be performed to other core chip. Further,a memory capacity (the number of memory cells) of a chip that isassigned by the refresh command REF for one time is reduced to ⅛ of aconventional memory capacity. Accordingly, the shortest issuing intervalof a refresh command can be shortened even when it is necessary tocomply with specifications such that a shortest issuing interval of arefresh command becomes long when a memory capacity of the semiconductormemory device 10 is larger. Specifically, while a shortest issuinginterval of a refresh command is 110 ns (tRFC=110 ns) when a memorycapacity is 1G in the DDR3 standard, the shortest issuing interval of arefresh command becomes 350 ns (tRFC=350 ns) when the memory capacity is8 Gb. The semiconductor memory device 10 according to the presentembodiment has a total memory capacity of 8 Gb. Therefore, a shortestissuing interval of a refresh command is basically 350 ns. However,because a memory capacity of a chip that is assigned by the refreshcommand REF for one time is ⅛ of the total memory capacity as describedabove, the semiconductor memory device 10 can issue a refresh command atan interval of 110 ns that is the same as the interval when a memorycapacity is 1 Gb.

FIG. 19 is a timing diagram for explaining an operation of thesemiconductor memory device 10 when the second operation mode isselected.

In an example shown in FIG. 19, at a time t10, the refresh command REFis issued for one time from outside. Further, in the second operationmode, the address information SIDADD relevant to issuing of the refreshcommand for one time is not input. In response to this, the refreshcontrol signal REFb is activated for four times in time series, and theactivated signals are supplied to all the core chips CC0 to CC7.However, in each core chip, the refresh control signal REFc is activatedonly when the signal corresponds to the refresh control signal REFb at apredetermined number of order out of the refresh control signal REFb forfour times in time series, by the comparison circuit 220 shown in FIG.12, as can be understood by an operation waveform of the comparisoncircuit 220 included in each of the core chips CC0 to CC7 shown in FIG.14. Therefore, as shown in FIG. 19, the refresh control signal REFc ofthe comparison circuit 220 included in each of the core chips CC0 to CC7is activated sequentially in the order of the two core chips CC0 andCC4, the two core chips CC1 and CC5, the two core chips CC2 and CC6, andthe two core chips CC3 and CC7. Accordingly, a refresh operation isperformed in all the core chips CC0 to CC7.

As described above, in the second operation mode, all the core chips CC0to CC7 perform a refresh operation corresponding to the refresh commandREF for one time from outside. Accordingly, unlike in the firstoperation mode, during a refresh operation period when all the corechips CC0 to CC7 are busy, a next command cannot be issued to thesemiconductor memory device 10 from outside. Similarly, the refreshcommand REF cannot be issued in the middle of a read operation or awrite operation. In the second operation mode, a shortest issuinginterval of a refresh command becomes 350 ns when a memory capacity is 8Gb. That is, a busy period is long unlike in the first operation mode.

In the first operation mode, only one core chip is refreshedcorresponding to the refresh command REF for one time. Therefore, ascompared with a setting in the second operation mode, an external devicethat controls the semiconductor memory device 10 needs to issue therefresh command REF at a frequency of eight times. However, it sufficesthat the external device issues the refresh command REF at a frequencyof the number of times of core chips (eight times in the presentembodiment) regardless of the number of banks (independent regions)included in one core chip. Therefore, the issuing frequency of therefresh command REF does not become excessively high. As a comparativeexample, according to a method of assigning one bank of one core chip bythe refresh command REF for one time, the external device needs to issuethe refresh command REF at a frequency of the number of banks (64 timesin the present embodiment) included in a core chip multiplied by thenumber of core chips. On the other hand, in the present embodiment, theissuing frequency of the refresh command REF does not become excessivelyhigh as described above.

FIG. 20 is a circuit diagram of the layer address comparison circuit 47included in each of the core chips CC0 to CC7 according to amodification.

The layer address comparison circuit 47 shown in FIG. 20 includescomparing units 400 to 402 that compare bits (SID0 to SID2) of the layeraddress SID with bits (SIDADD0 to SIDADD2) of the address informationSIDADD, respectively, and a NAND gate circuit 403 that receives outputsof the comparing units 400 to 402. An output of the NAND gate circuit403 is used as the enable signal SIDEN.

A mode selection signal REFSd is input in addition to the layer addressSID2 and the address information SIDADD2, to the comparing unit 402. Themode selection signal REFSd is supplied from the mode register 64. Whenthe mode selection signal REFSd is at a low level, a single slice modeis obtained in which only one core chip is refreshed per the refreshcommand REF for one time in the first operation mode. When the modeselection signal REFSd is at a high level, a double slice mode isobtained in which only two core chips are refreshed per the refreshcommand REF for one time in the first operation mode.

In the case of the single slice mode, when the bits SID0 to SID2 of thelayer address SID and the bits SIDADD0 to SIDADD2 of the addressinformation SIDADD all match each other, the enable signal SIDEN isactivated. Therefore, the enable signal SIDEN is activated in only onecore chip. On the other hand, in the case of the double slice mode, acomparison operation by the comparing unit 402 is invalidated, and adetermination of a match is forcibly made. As a result, the enablesignal SIDEN is activated in two core chips. Combinations of two corechips to be activated are fixed, and the core chips CC0 and CC4, thecore chips CC1 and CC5, the core chips CC2 and CC6, and the core chipsCC3 and CC7 become pairs, respectively.

FIG. 21 is a timing diagram for explaining an operation in the doubleslice mode. The operation in the single slice mode is as explained withreference to FIG. 18.

As shown in FIG. 21, when the refresh command REF and the addressinformation SIDADD for assigning the core chip CC0 are input fromoutside at the time to, the refresh control circuit included in each ofthe core chips CC0 and CC4 activates a corresponding refresh controlsignal REFc for one time in the core chips CC0 and CC4. Accordingly, arefresh operation is performed simultaneously in the core chips CC0 andCC4. When the refresh command REF and the address information SIDADD forassigning the core chip CC1 are input from outside at the time t2, therefresh control circuit included in each of the core chips CC1 and CC5activates a corresponding refresh control signal REFc for one time inthe core chips CC1 and CC5. Accordingly, a refresh operation isperformed in the core chips CC1 and CC5. A simultaneous selection of twocore chips also includes that the memory cell arrays 50 relevant to thetwo core chips respectively access simultaneously or that operationcurrents of the memory cell arrays 50 relevant to the two core chipsrespectively are delayed so as to be slightly shifted each other. Forexample, the simultaneous selection of two core chips includes adelaying of slightly shifting the operation currents of the sensecircuits 53 relevant to the two banks respectively corresponding to therefresh control signal REFd for one time. These operations are valid toreduce noise within the semiconductor memory device 10.

As described above, in the double slice mode, because the highest-orderbit SIDADD2 of the address information SIDADD is invalidated in arefresh operation, two core chips can be refreshed by the refreshcommand REF for one time even in the first operation mode. Accordingly,the issuing frequency of the refresh command REF can be set lower.However, in the double slice mode, because two core chips are refreshedsimultaneously, six core chips can be accessed out of eight core chipsin the refresh operation.

When the number of bits of the address information SIDADD to beinvalidated in the refresh operation is increased, the number of corechips to be refreshed by the refresh command REF for one time can beincreased. For example, when the address information SIDADD1 and SIDADD2are invalidated, four core chips can be refreshed by the refresh commandREF for one time.

A second embodiment of the present invention is explained next.

FIG. 22 is a circuit diagram of a refresh-control-signal generationcircuit 100 a included in the interface chip IF that is used in a secondembodiment of the present invention. The refresh-control-signalgeneration circuit 100 a is used instead of the refresh-control-signalgeneration circuit 100 shown in FIG. 7.

As shown in FIG. 22, a self-refresh state signal PSELF and a clockenable signal PCKE are used in the refresh-control-signal generationcircuit 100 a. The self-refresh state signal PSELF becomes at a highlevel when a self-refresh entry command is issued from outside, and thissignal shows a state that the semiconductor memory device 10 is in aself-refresh mode. The clock enable signal PCKE is an internal commandand the clock enable signal CKE supplied from outside is buffered. Whenthe self-refresh entry command is issued, the clock enable signal CKEimmediately becomes at a low level.

The self-refresh state signal PSELF and the clock enable signal CKE areinput to an OR gate circuit 150, and an output of the OR gate circuit150 is input to a complex gate circuit 151. The complex gate circuit 151corresponds to the OR gate circuit 145 shown in FIG. 7, and an output ofthe complex gate circuit 151 is used as the refresh control signal REFb.As described above, because the clock enable signal CKE becomes a lowlevel when a self-refresh entry command is input, activation of therefresh control signal REFb is prohibited until the self-refresh statesignal PSELF changes to a high level. Therefore, activation of theinternal refresh command REFa at a first time is invalidated. When theself-refresh state signal PSELF changes to a high level to compensatefor the invalidation, a one-shot-pulse generation circuit 152 generatesa one-shot signal, and activates the refresh control signal REFb via anOR gate circuit 153. At the same time, the SR latch circuit 140 is set,and an operation similar to that of the second operation mode is startedregardless of the mode selection signal PRA. That is, therefresh-control-signal generation circuit 100 a generates the refreshcontrol signal REFb for four times each time when the internal refreshcommand REFa is activated.

Thereafter, the refresh control signal REFb is activated for four timeseach time when the internal refresh command REFa is activated, theinternal refresh command REFa being periodically and automaticallygenerated asynchronously with outside of the semiconductor memory device10 by a refresh timer (not shown) that is included in the interface chipIF.

FIG. 23 is a circuit diagram of the refresh control circuit 200 aincluded in each of the core chips CC0 to CC7 that is used in the secondembodiment. The refresh control circuit 200 a is used instead of therefresh control circuit 200 shown in FIG. 12.

As shown in FIG. 23, in the refresh control circuit 200 a, an inversionsignal of the self-refresh state signal PSELF is supplied to an AND gatecircuit 233. Therefore, the enable signal REFEN as an output of thecomplex gate circuit 230 is normally activated only when the modeselection signal PRA is equal to H and when the self-refresh statesignal PSELF is equal to L. That is, even in the first operation mode,normal activation of the enable signal REFEN is cancelled when thesemiconductor memory device 10 enters the self-refresh mode. The enablesignal REFEN is activated only when the comparison circuit 220 detects amatch. The self-refresh state signal PSELF is also supplied to the layeraddress comparison circuit 47.

FIG. 24 is a circuit diagram of a layer address comparison circuit 47 aincluded in each of the core chips CC0 to CC7 and that is used in thesecond embodiment. The layer address comparison circuit 47 a is usedinstead of the layer address comparison circuit 47 shown in FIG. 20.

The layer address comparison circuit 47 a shown in FIG. 24 includes aninverter 405 that inverts the self-refresh state signal PSELF, and aNAND gate circuit 404 that receives an output of the inverter 405 and anoutput of the NAND gate circuit 403, in addition to the layer addresscomparison circuit 47 shown in FIG. 20. An output of the NAND gatecircuit 404 is used as the enable signal SIDEN. Based on a configurationdescribed above, the enable signal SIDEN is forcibly set at a high levelwhen the self-refresh state signal PSELF is at a high level.

As explained above, according to the second embodiment, even when thefirst operation mode is selected, the semiconductor memory device 10performs a refresh operation similar to that in the second operationmode when the semiconductor memory device 10 enters the self-refreshmode. Therefore, all the core chips CC0 to CC7 can be refreshed withoutgenerating the address information SIDADD within the semiconductormemory device 10.

FIG. 25 shows a configuration of a data processing system that uses thesemiconductor memory device 10 according to the embodiment.

The data processing system shown in FIG. 25 is constituted by thesemiconductor memory device 10 and a memory controller 500 that isconnected to the semiconductor memory device 10. The memory controller500 includes a refresh-command issuing circuit (first circuit) 510 thatissues a refresh command for plural times during a predetermined period,and periodically issues the refresh command REF to the semiconductormemory device 10. The memory controller 500 also includes anaddress-information issuing circuit 520 that issues the addressinformation SIDADD. When the semiconductor memory device 10 is in thefirst operation mode, the address-information issuing circuit 520 issuesthe address information SIDADD each time when the refresh-commandissuing circuit 510 issues a refresh command. On the other hand, thememory controller 500 does not issue a bank address when the refreshcommand REF is issued. This is because a bank address relevant to arefresh operation is automatically generated by the refresh counter 61 bwithin the core chips CC0 to CC7. Whether the semiconductor memorydevice 10 is to be set in the first operation mode or the secondoperation mode is set by an operation-mode setting circuit (thirdcircuit) 530 included in the memory controller 500.

As already explained above, when the semiconductor memory device 10 isset in the first operation mode, one or two or more core chips that areassigned by the address information SIDADD are selectively refreshed.Therefore, the number of times that the refresh command REF is issued bythe refresh-command issuing circuit 510 during a predetermined period isgreater when the semiconductor memory device is set in the firstoperation mode than when the semiconductor memory device 10 is set inthe second operation mode.

Specifically, when the semiconductor memory device 10 is set in thefirst operation mode and also when only one core chip is refreshed inresponse to the refresh command REF for one time (see FIG. 18), therefresh command REF needs to be issued at a frequency of eight times(=2³) of a case when the semiconductor memory device 10 is set in thesecond operation mode. When the semiconductor memory device is set inthe first operation mode and also when only two core chips are refreshedin response to the refresh command REF for one time (see FIG. 21), therefresh command REF needs to be issued at a frequency of four times(=2²) of a case when the semiconductor memory device 10 is set in thesecond operation mode. As described above, the number of times when therefresh-command issuing circuit 510 needs to issue the refresh commandREF during a predetermined period when the semiconductor memory device10 is set in the first operation mode becomes a power of two of thenumber of times when the refresh-command issuing circuit 510 needs toissue the refresh command REF during a predetermined period when thesemiconductor memory device 10 is set in the second operation mode.

In a normal access, the memory controller 500 supplies a read command ora write command to the command terminal 12 of the semiconductor memorydevice 10, and supplies the address signal ADD to the address terminal13. Accordingly, read data DQ is supplied to the memory controller 500from the data input/output terminal 14 of the semiconductor memorydevice 10 in a read operation, and the memory controller 500 supplieswrite data DQ to the data input/output terminal 14 of the semiconductormemory device 10 in a write operation.

It is apparent that the present invention is not limited to the aboveembodiments, but may be modified and changed without departing from thescope and spirit of the invention.

For example, although a DDR3 SDRAM is used as a core chip in theembodiments described above, the SDRAM used in the present invention isnot limited thereto. Therefore, it suffices to use a DRAM other than aDDR3 SDRAM, and a semiconductor memory other than a DRAM is alsoacceptable as far as the semiconductor memory is of a type that requiresa refresh operation. It is not essential that all core chips arestacked, and a part or the whole of core chips can be arranged in aplane. Further, the number of core chips is not limited to eight.

In the embodiments described above, although the mode selection signalPRA to be used in each of the core chips CC0 to CC7 is supplied from themode register 64 within a corresponding core chip, the mode selectionsignal PRA can be supplied to each of the core chips CC0 to CC7 from themode register 42 within an interface chip. Further, the mode selectionsignal PRA does not need to be switchable by the memory controller 500,and a manufacturer of a semiconductor memory device can fix an operationmode at a manufacturing stage of the semiconductor memory device byusing a ROM or the like.

In the embodiments described above, although the refresh-control-signaldividing circuit 300 included in each of the core chips CC0 to CC7 isused to refresh eight banks for four times separately in response toactivation of the refresh control signal REFc that is generated by eachof the core chips CC0 to CC7, a refresh method of the eight banks is notparticularly limited. The eight banks can be refreshed for eight timesseparately for each one bank, or can be refreshed for two timesseparately for each four banks, or the eight banks can be refreshedsimultaneously.

In the embodiments described above, when the semiconductor memory device10 is set in the second operation mode, the refresh control signal REFbgenerated by the interface chip IF is activated for four times inresponse to the internal refresh command REFa for one time generated bythe interface chip IF. However, so long as all the core chips CC0 to CC7are refreshed, there is no particular limit to the number of times whenthe refresh control signal REFb generated by the interface chip IF isactivated. Specifically, when the number of core chips is m, in thesecond operation mode, it suffices that the refresh-control-signalgeneration circuit 100 included in the interface chip IF activates therefresh control signal REFb at m/2′ times (n is an integer equal to orlarger than 0) in response to the internal refresh command REFa. Withthis arrangement, all the core chips CC0 to CC7 can be refreshedsimultaneously.

In addition, while not specifically claimed in the claim section, theapplicant reserves the right to include in the claim section of theapplication at any appropriate time the following devices:

A1. A memory controller that controls a semiconductor memory deviceincluding an interface chip and a plurality of core chips, the memorycontroller comprising:

a first circuit that issues a refresh command at a plurality of timesduring a predetermined period; and

a second circuit that issues address information that selects the corechips along with the refresh command.

A2. The memory controller as A1, further comprising

a plurality of memory cells provided in each of the core chips areclassified into a plurality of independent regions that are mutuallynon-exclusively controlled, wherein the memory controller does not issuea bank address that selects one of the independent regions along withthe refresh command.

A3. The memory controller as A1, further comprising a third circuit thatsets the semiconductor memory device in one of a first operation modeand a second operation mode, wherein

a number of times in which the first circuit issues the refresh commandduring the predetermined period on the semiconductor memory device isset in the first operation mode is greater than a number of times inwhich the first circuit issues the refresh command during thepredetermined period on the semiconductor memory device is set in thesecond operation mode.

A4. The memory controller as A3, wherein the number of times in whichthe first circuit issues the refresh command during the predeterminedperiod on the semiconductor memory device is set in the first operationmode is a power of two of the number of times in which the first circuitissues the refresh command during the predetermined period on thesemiconductor memory device is set in the second operation mode.

A5. The memory controller as A3, wherein on the semiconductor memorydevice is set in the second operation mode, the memory controller doesnot supply the address information that selects the core chip along withthe refresh command.

A6. The memory controller as A2, further comprising a third circuit thatsets the semiconductor memory device in one of a first operation modeand a second operation mode, wherein

a number of times in which the first circuit issues the refresh commandduring the predetermined period on the semiconductor memory device isset in the first operation mode is greater than a number of times inwhich the first circuit issues the refresh command during thepredetermined period on the semiconductor memory device is set in thesecond operation mode.

A7. The memory controller as A6, wherein the number of times in whichthe first circuit issues the refresh command during the predeterminedperiod on the semiconductor memory device is set in the first operationmode is a power of two of the number of times in which the first circuitissues the refresh command during the predetermined period on thesemiconductor memory device is set in the second operation mode.

A8. The memory controller as A6, wherein when the semiconductor memorydevice is set in the second operation mode, the memory controller doesnot supply the address information that selects the core chip along withthe refresh command.

What is claimed is:
 1. A memory controller that controls a semiconductormemory device including an interface chip and a plurality of core chips,the memory controller comprising: a first circuit that issues a refreshcommand at a plurality of times during a predetermined period; and asecond circuit that issues address information that selects the corechips along with the refresh command.
 2. The memory controller asclaimed in claim 1, further comprising a plurality of memory cellsprovided in each of the core chips are classified into a plurality ofindependent regions that are mutually non-exclusively controlled,wherein the memory controller does not issue a bank address that selectsone of the independent regions along with the refresh command.
 3. Thememory controller as claimed in claim 1, further comprising a thirdcircuit that sets the semiconductor memory device in one of a firstoperation mode and a second operation mode, wherein a number of times inwhich the first circuit issues the refresh command during thepredetermined period on the semiconductor memory device is set in thefirst operation mode is greater than a number of times in which thefirst circuit issues the refresh command during the predetermined periodon the semiconductor memory device is set in the second operation mode.4. The memory controller as claimed in claim 3, wherein the number oftimes in which the first circuit issues the refresh command during thepredetermined period on the semiconductor memory devise is set in thefirst operation mode is a power of two of the number of times in whichthe first circuit issues the refresh command during the predeterminedperiod on the semiconductor memory device is set in the second operationmode.
 5. The memory controller as claimed in claim 3, wherein on thesemiconductor memory device is set in the second operation mode, thememory controller does not supply the address information that selectsthe core chip along with the refresh command.
 6. The memory controlleras claimed in claim 2, further comprising a third circuit that sets thesemiconductor memory device in one of a first operation mode and asecond operation mode, wherein a number of times in which the firstcircuit issues the refresh command during the predetermined period onthe semiconductor memory device is set in the first operation mode isgreater than a number of times in which the first circuit issues therefresh command during the predetermined period on the semiconductormemory device is set in the second operation mode.
 7. The memorycontroller as claimed in claim 6, wherein the number of times in whichthe first circuit issues the refresh command during the predeterminedperiod on the semiconductor memory device is set in the first operationmode is a power of two of the number of times in which the first circuitissues the refresh command during the predetermined period on thesemiconductor memory device is set in the second operation mode.
 8. Thememory controller as claimed in claim 6, wherein when the semiconductormemory device is set in the second operation mode, the memory controllerdoes not supply the address information that selects the core chip alongwith the refresh command.